Semiconductor device fabrication often involves deposition of conductive materials for front end of line (FEOL), middle of line (MOL) and back end of line (BEOL) applications such as source and drain contacts and logic interconnects. For example, tungsten-containing materials may be used for horizontal interconnects, vias between adjacent metal layers, and contacts between first metal layers and devices on the silicon substrate. Copper is another commonly used conductive material. However, as devices shrink, features become narrower and aspect ratios increase, resulting in challenges in employing these conductive materials.
For example, copper interconnects are challenging to fabricate beyond the 7 nm technology node. Deposition of copper interconnects often involves first depositing a barrier layer. A copper barrier material that maintains its integrity as thickness is scaled below 2.5 nm has not been identified. As the linewidth scales to 10 nm (at the 5 nm technology node), the barrier will consume 5 nm of the linewidth and more than 50% of the line cross-section, increasing the resistance exponentially with each technology node beyond 10 nm. As a result, alternative materials are sought to fill features.
One alternative to copper and tungsten is cobalt. However, there are various process integration challenges for applications such as cobalt interconnects.